1. Field of the Invention
The present invention relates to an overlay mark that is used in the step of lithography during a manufacturing process of a semiconductor device, a liquid crystal panel or the like, to measure the overlay accuracy between patterns formed on a substrate, or to make alignment in superimposing a mask onto a wafer at the time of exposure. Further, the present invention relates to a method of measuring the overlay accuracy and a method of making alignment, with such marks being utilized, and also relates to a semiconductor device having a substrate on which such marks are formed.
2. Description of the Related Art
In lithographic techniques employed for the production of a semiconductor device, a liquid crystal panel and the like, it is particularly important to form a minute pattern with precision and, at the same time, superimpose this pattern onto an underlying layer with accuracy.
For this purpose, in the step of lithography during these manufacturing processes, when a second circuit pattern is formed to overlay a first circuit pattern, alignment to superimpose a mask onto a wafer is made at the time of exposure and, then, after patterning is carried out by means of exposure and development, the overlay accuracy between the patterns formed in this manner is measured.
Once the overlay accuracy between the formed patterns is measured, patterns having a defective overlay accuracy, that is, patterns between which the overlay deviation is above a prescribed value are removed, and thereby the success rate of pattern formation is improved. This underlines the importance of the accurate measurement of the overlay accuracy.
To measure this overlay accuracy, various overlay mark with patterns have been hitherto being utilized (Japanese Patent Application Laid-open No. 251945/1997, No. 160413/1998 and such). Typical examples, each with a top view and a cross-sectional view, are shown in FIGS. 12-15. FIG. 12 presents a box-in-box type mark; FIG. 13, a frame-in-box type mark; FIG. 14, a frame-in-frame type mark and FIG. 15, a bar-in-bar type mark.
A box-in-box type mark has a depressed lower-layer pattern 1 in the shape of a quadrangle viewed from the top, and an upper-layer pattern 2 with a quadrangular top that is smaller than the lower-layer pattern 1 and formed inside of that, as shown in FIG. 12.
A frame-in-box type mark has a lower-layer pattern 1 in the shape of a quadrangular frame viewed from the top, and an upper-layer pattern 2 with a quadrangular top that is smaller than the lower-layer pattern 1 and formed inside of that, as shown in FIG. 13.
A frame-in-frame type mark has a lower-layer pattern 1 in the shape of a quadrangular frame viewed from the top, and an upper-layer pattern 2 in the shape of a quadrangular frame that is smaller than the lower-layer pattern 1 and formed inside of that, as shown in FIG. 14.
A bar-in-bar type mark has a lower-layer pattern 1 in which four bar-shaped patterns are each disposed in place of a side of a quadrangle, and an upper-layer pattern 2 that is similar in shape and formed inside of the lower-layer pattern 1, as shown in FIG. 15.
In any of these marks, the lower-layer pattern 1 is formed by engraving an underlying layer 3 and the upper-layer pattern 2 is formed with a resist layer that is formed on an upper layer 4 laid over the underlying layer 3.
The upper-layer pattern 2 in the box-in-box type mark and in the frame-in-box type mark, shown in FIG. 12 and FIG. 13, respectively, are each formed by laying a quadrangular prism of resist block on the upper layer 4. However, an upper-layer pattern in these marks can be formed negatively by providing as depressed section (an indent) or an opening section in the shape of a polygon on a resist layer. The upper-layer pattern 2 in the frame-in-frame type mark and in the bar-in-bar type mark, shown in FIG. 14 and FIG. 15, respectively, are each formed by engraving a grooved pattern in the shape of a frame or bars on a resist layer 2a. However, an upper-layer pattern in these marks can be formed of resist block in the shape of a frame or bars.
To measure the overlay accuracy with an overlay mark of this sort, the lower-layer pattern is first formed onto the underlying layer 3 and, then, after the upper layer 4 is formed over this underlying layer 3, the upper-layer pattern 2 is formed with the resist layer that is applied thereto. Using both of these lower-layer pattern 1 and upper-layer pattern 2, the overlay accuracy is measured. For the measurement of the overlay accuracy, an optical image-processing type overlay measuring apparatus is normally used and the light intensity profile of the reflected light travelling from the overlay mark for measuring the overlay accuracy is obtained. The central positions of the lower-layer pattern and upper-layer pattern are each calculated from the light intensity profile and a shift between these central positions is taken as the overlay accuracy.
Meanwhile, in the step of exposure in which circuit patterns formed on a plurality of masks are transcribed onto a single semiconductor wafer using a stepper, an electron beam exposure system or the like, what is important is that, in order to prevent relative positions between transcribed patterns from shifting, the positions of each mark and the wafer must be aligned with a high accuracy, or, in other words, the alignment accuracy must be kept high.
A method to align a wafer and a mask, for example, proceeds as follows. Firstly, an overlay mark (an alignment mark) to recognize a prescribed position of a wafer is formed on the wafer, and, with this alignment mark being irradiated with a light or an electron beam, the position of the alignment mark is detected, making use of the diffracted light or reflected electrons from the alignment mark, and, then, on the basis of this detected position, an appropriate alignment is made by moving an X-Y stage. Such an alignment mark is formed in a prescribed position of a dicing line of the wafer or such, by engraving an underlying layer by means of etching, with a pattern shown in FIG. 16, for example, a line and space pattern (FIG. 16(a)) comprising bar-shaped grooves, a pattern of a plurality of parallel arrays (FIG. 16(b)) each of which is a pattern comprising square indents in a line, or the like (Japanese Patent Application Laid-open No. 42128/1989, No. 4044/1998 and such). Through the detection of the position of such an alignment mark comprising grooves or indents, the alignment is made.
However, in recent years, accompanied with achievement of further miniaturization and more densely-placed arrangement of elements, the standard required for the overlay accuracy has been rising. With the conventional overlay mark described above, it has become considerably difficult to satisfy demands that the measurement of the overlay accuracy and the alignment should be made with a sufficient accuracy to fit recent technical developments.
The overlay mark is generally formed on a dicing line. However, as the arrangement of elements becomes still more densely spaced, this overlay mark has become formed much closer to a circuit pattern. Around the overlay mark that is formed close to a circuit pattern, variation in structural environment may arise. When a heating during the manufacturing process brings about thermal expansion or contraction of the layer on which the mark is formed, the overlay mark may undergo non-uniform deformation due to difference in the extent of expansion or contraction resulting from this variation in structural environment. The deformation of this kind caused by thermal expansion or contraction is particularly pronounced, when the layer on which the overlay mark is formed is a film having an amorphous structure such as a BPSG (Boro-Phospho-Silicate Glass) film, a CVD (Chemical Vapour Deposition) silicon oxide film or the like. The deformation of the overlay mark reduces the alignment accuracy and the accuracy of measurement for the overlay accuracy, and lowers the yield and the quality of the products and, therefore, with miniaturization proceeding, it has become a problem of utmost importance.
The deformed state of an overlay mark is schematically shown in FIG. 17, taking the case of the frame-in-box type overlay mark shown in FIG. 13. FIG. 17(a) is a plan view and FIG. 17(b), a cross-sectional view taken along the line A-A of FIG. 17(a).
While no pattern but the pattern for the overlay mark is present in the vicinity of the left section 1a of the lower-layer pattern 1, a pattern 5 for an adjacent circuit is disposed close to the right section 1b of the lower-layer pattern 1. When a heating is applied to this pattern layout, the amount of thermal contraction of the underlying layer lying in the region on the left of the lower-layer pattern 1a is greater than the amount of thermal contraction of the underlying layer lying in the small region contained between the lower-layer pattern 1b and the adjacent circuit pattern 5 so that the lower-layer pattern 1a deforms badly. Consequently, the position of the lower-layer pattern cannot be located accurately and the accuracy of the measurement for the overlay accuracy is lowered. The same happens in the box-in-box type mark, the frame-in-frame type mark, the bar-in-bar type mark and the alignment mark.
An object of the present invention is to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern.
The present invention relates to an overlay mark having a mark pattern formed by engraving a groove or an indent in a prescribed position on a layer where a circuit pattern is formed, and a grooved pattern that surrounds said mark pattern so as to protect said mark pattern from being deformed by thermal expansion or contraction of said layer.
Further, the present invention relates to an overlay mark used for measuring the overlay accuracy in forming a second circuit pattern over a first circuit pattern; which has:
a first lower-layer pattern formed by engraving a groove or an indent in a prescribed position on a first layer where the first circuit pattern is formed, and an upper-layer pattern formed in a prescribed position on a second layer where the second circuit pattern is to be formed; and, in addition,
a second lower-layer pattern that is formed by engraving, on the first layer, a frame-shaped groove to surround the first lower-layer pattern, and is not used for measuring the overlay accuracy.
Further, the present invention relates to an overlay mark used for making alignment to detect and decide an aligning position of a wafer and a mask, in the step of exposure during photolithography to form a second circuit pattern over a first circuit pattern; which has:
a first pattern formed by engraving a groove or an indent in a prescribed position on a layer where the first circuit pattern is formed; and
a second pattern that is formed by engraving a frame-shaped groove to surround the first pattern, and is not used for making alignment.
Further, the present invention relates to a semiconductor device having a substrate on which the overlay mark of the present invention described above is formed.
Further, the present invention relates to a method of measuring the overlay accuracy in forming a second circuit pattern over a first circuit pattern, wherein the overlay mark of the present invention described above is used but, at least, the outermost lower-layer pattern is not utilized to detect an overlay position.
Further, the present invention relates to a method of making alignment to detect and decide an aligning position of a wafer and a mask, in the step of exposure during photolithography to form a second circuit pattern over a first circuit pattern, wherein the overlay mark of the present invention described above is used but, at least, the outermost pattern is not utilized to detect an aligning position.
The present invention enables to form a multi-layered circuit pattern with a high accuracy and a high yield in production, even in the formation of a minute and densely-spaced circuit pattern for a semiconductor device, a liquid crystal panel or the like.
The present invention is particularly well suited for the case in which the first layer where the first circuit pattern is formed is a thermally soft film with an amorphous structure, for example, a CVD oxide film or an oxide glass containing boron and phosphuorus, such as a BPSG film or the like.